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Proceedings Paper

VLSI components for a 560-Mbit/s HDTV codec
Author(s): Klaus Grueger; Peter Pirsch; Josef Kraus; Jochen Reimers
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Paper Abstract

The hardware implementation of a DPCM coding algorithm with 2D prediction, noise shaping and fixed codeword length for the transmission of HDTV signals with 560 Mbit/s bit rate has been investigated. In order to reduce timing requirements an architecture with parallel processing elements and with modified DPCM-structure is proposed. DPCM and FIFO circuits as major components for such a codec have been designed for a VLSI-realization using 1.2|im CMOS technology.

Paper Details

Date Published: 1 September 1990
PDF: 10 pages
Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24226
Show Author Affiliations
Klaus Grueger, Univ. Hannover (Germany)
Peter Pirsch, Univ. Hannover (Germany)
Josef Kraus, Deutschen Bundespost TELEKOM (Germany)
Jochen Reimers, Deutschen Bundespost TELEKOM (Germany)

Published in SPIE Proceedings Vol. 1360:
Visual Communications and Image Processing '90: Fifth in a Series
Murat Kunt, Editor(s)

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