In this paper we examine the use of a recent innovation, called the logarithmic residue number system or LRNS, as an alternative to conventional DSP processors for implementing multiply-accumulate operations. We have fabricated a custom VLSI processor based upon this technology that is capable of providing substantial acceleration of vector arithmetic operations, convolution, correlation, and Fourier transforms in a relatively small, fast processor core when compared with implementations based on conventional arithmetic. The constituent arithmetic elements can be used as standard cells to implement application specific DSP designs.

Date Published: 7 June 1996
PDF: 12 pages
Proc. SPIE 2750, Digital Signal Processing Technology, (7 June 1996); doi: 10.1117/12.241986

Published in SPIE Proceedings Vol. 2750:
Digital Signal Processing Technology
Joseph Picone, Editor(s)