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Proceedings Paper

SCC-100 parallel processor for real-time imaging
Author(s): William J. Jacobi; William B. Kendall; Leo A. Wadsworth
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Paper Abstract

The SCC-100 parallel processor utilizes a fully-programmable, 32-bit MIMD architecture optimized for image and signal processing. Applications include image registration, clutter suppression, velocity filtering, multispectral processing, medical imaging and computer vision research as well as radar and sonar signal processing. The first SCC-100 processor, with 19 nodes and a peak throughput in excess of 1 GFLOPS, was recently delivered. A micro-miniature version using hybrid wafer-scale integration is currently under development for space applications.

Paper Details

Date Published: 1 September 1990
PDF: 5 pages
Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24131
Show Author Affiliations
William J. Jacobi, Space Computer Corp. (United States)
William B. Kendall, Space Computer Corp. (United States)
Leo A. Wadsworth, Space Computer Corp. (United States)

Published in SPIE Proceedings Vol. 1360:
Visual Communications and Image Processing '90: Fifth in a Series
Murat Kunt, Editor(s)

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