Share Email Print

Proceedings Paper

Patterning ULSI circuits
Author(s): John R. Carruthers
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The traditional scaling of feature sizes to ever smaller dimensions which has driven the semiconductor industry for 30 years is being challenged by physical and cost limits. As we approach the development of the 180 nm generation, we have a quite different technology scenario facing us than we have seen in the past. The approaches being contemplated can be summarized in order of utility as: (1) extensions of existing patterning methods; (2) non- lithography patterning approaches; (3) extensions of the optical projection/reduction approach; (4) new beam techniques; and (5) probe techniques. I review the challenges in each of these categories and indicate where serious development efforts are needed to sustain technology scaling into the ULSI generations.

Paper Details

Date Published: 21 May 1996
PDF: 13 pages
Proc. SPIE 2725, Metrology, Inspection, and Process Control for Microlithography X, (21 May 1996); doi: 10.1117/12.240078
Show Author Affiliations
John R. Carruthers, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 2725:
Metrology, Inspection, and Process Control for Microlithography X
Susan K. Jones, Editor(s)

© SPIE. Terms of Use
Back to Top