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Proceedings Paper

VLSI gray-scale morphology processor for real-time NDE image-processing applications
Author(s): Marwan M. Hassoun; Trevor E. Meyer; P. R. Siqueira; John P. Basart; Suresh Gopalratnam
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Paper Abstract

This paper describes the VLSI hardware implementation onto an ASIC (Application Specific Integrated Circuit) of a gray-scale morphology processor. This is a prototype first chip of a series for a project to perform real-time image processing for NDE (Non-Destnicve Evaluation) applications. Processing of images requires the performance of relatively simple mathematical operations like additions subtractions and comparisons on a tremendously large amount of pixels (data points). This hardware implementation uses the idea of an array processor where each processor performs the exact same operations at the same time but on different pixels. The morphology operation is done in a highly parallel fashion thus enabling a real time performance of 80 MOPS (Million Operations Per Second). The chip described in this paper has the capability of performing both erosion and dilation operations on variable size images with a variable size structuring element. This custom chip was designed using a 2. t CMOS process on a die size of 6. 8 x 6. 9 mm2 in the Department of Electrical Engineering and Computer Engineering at Iowa State University. Custom layout was chosen over standard cell implementation in order to reduce the area of the chip and to increase the operational speed. The fabrication is being done through the MOSIS fabrication services. For the project the final version of the chip will be implemented in a 1jt CMOS technology thus enhancing the speed and

Paper Details

Date Published: 1 November 1990
PDF: 10 pages
Proc. SPIE 1350, Image Algebra and Morphological Image Processing, (1 November 1990); doi: 10.1117/12.23605
Show Author Affiliations
Marwan M. Hassoun, Iowa State Univ. (United States)
Trevor E. Meyer, Iowa State Univ. (United States)
P. R. Siqueira, Iowa State Univ. (United States)
John P. Basart, Iowa State Univ. (United States)
Suresh Gopalratnam, Iowa State Univ. (United States)

Published in SPIE Proceedings Vol. 1350:
Image Algebra and Morphological Image Processing
Paul D. Gader, Editor(s)

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