Share Email Print

Proceedings Paper

Model and algorithm for VHDL high-level and hierarchical simulation with debug function
Author(s): Jinain Bian; Feng Lu; Bo Wan; Ming Su
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A VHDL simulator with debug function will play a very important role in the area of hardware description and design. The debug function makes the simulation model and the algorithm much more complicated, and sets a still higher demand on the simulator. In this paper an effective hierarchical model and a simulation algorithm suited to debug function requirement are proposed. The hierarchical model and the algorithm support a whole set of VHDL, including behavioral structural and data flow description manner, all kinds of data types of signals and variables, hierarchical component configuration and subprogram call, and to support many kinds of interrupt requirement, on time, condition, component, process, subprogram and statement line.

Paper Details

Date Published: 22 March 1996
PDF: 6 pages
Proc. SPIE 2644, Fourth International Conference on Computer-Aided Design and Computer Graphics, (22 March 1996); doi: 10.1117/12.235495
Show Author Affiliations
Jinain Bian, Tsinghua Univ. (China)
Feng Lu, Tsinghua Univ. (China)
Bo Wan, Tsinghua Univ. (China)
Ming Su, Tsinghua Univ. (China)

Published in SPIE Proceedings Vol. 2644:
Fourth International Conference on Computer-Aided Design and Computer Graphics
Shuzi Yang; Ji Zhou; Cheng-Gang Li, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?