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Proceedings Paper

Improvement of VLSI architecture for two-dimensional discrete cosine transform and its inverse
Author(s): Kyeounsoo Kim; Soon Hwa Jang; Soon Hong Kwon; Kyung Sik Son
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Paper Abstract

This paper presents an improvement of VLSI architecture for 2-dimensional DCT (discrete cosine transform) and its inverse in complexity and speed. In the proposed architecture, an accuracy compensator and a bit serial transposition network are newly introduced. It can be easily applied to the previously developed 2-D DCT/IDCT architectures, and revised to more fast and simple architecture without changing the existing scheme. Its other main characteristic is that this scheme jumps over the restriction of the computational resolution for the finite word length calculation. Bit serial transposition network needs less registers and more simple routing than the existing architectures. The proposed architecture shows operation speed over 100 MHz in 0.6 micrometer 3-metal CMOS technology.

Paper Details

Date Published: 27 February 1996
PDF: 10 pages
Proc. SPIE 2727, Visual Communications and Image Processing '96, (27 February 1996); doi: 10.1117/12.233318
Show Author Affiliations
Kyeounsoo Kim, Korea Telecom Research Ctr. (South Korea)
Soon Hwa Jang, Korea Telecom Research Ctr. (South Korea)
Soon Hong Kwon, Korea Telecom Research Ctr. (South Korea)
Kyung Sik Son, Pusan National Univ. (South Korea)

Published in SPIE Proceedings Vol. 2727:
Visual Communications and Image Processing '96
Rashid Ansari; Mark J. T. Smith, Editor(s)

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