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Proceedings Paper

Architectures for high-speed re-synchronization using parallel pattern matching
Author(s): Sanghoon Lee; Soon Hwa Jang; Soon Hong Kwon
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Paper Abstract

A variable length coder adds a synchronization code having a fixed length to a bit stream for fast resynchronization after transmission error or random access. In this paper, we present architectures for high speed resynchronization with a desired bit pattern such as synchronization code from an input bit stream. We consider the hardware architecture for achieving parallel pattern matching and apply it to VLD of the video decoder. The hardware architectures are constructed to minimize the time taken for one stage in the system for finding match pattern. It can rapidly deal with the transmission error and random access through high speed resynchronization.

Paper Details

Date Published: 27 February 1996
PDF: 8 pages
Proc. SPIE 2727, Visual Communications and Image Processing '96, (27 February 1996); doi: 10.1117/12.233312
Show Author Affiliations
Sanghoon Lee, Korea Telecom Research Ctr. (South Korea)
Soon Hwa Jang, Korea Telecom Research Ctr. (South Korea)
Soon Hong Kwon, Korea Telecom Research Ctr. (South Korea)


Published in SPIE Proceedings Vol. 2727:
Visual Communications and Image Processing '96
Rashid Ansari; Mark J. T. Smith, Editor(s)

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