In the real-time image processing system, SRIO was used to meet the demands of massive data interacting capacity between FPGA and DSP. This paper realized the massive image data transmission between FPGA and DSP with SRIO. The image sensor outputs image data in 4 channels and the clock in each channel is 175MHz, five times of input clock. Since the data channel is double data rate, so the data rate of one channel is 350Mbps, the data rate of the whole image sensor is 1400Mbps. FPGA receives the sampled data from image sensor and reorganizes the image data, and then transmits the organized data to camera link interface for display testing on the one hand; on the other hand, FPGA transmits the sorted data to DSP via SRIO for further process. The SRIO transmission between FPGA and DSP uses x1 mode, 8b/10b coding, and the transmission rate is 2.5Gbps per lane. The result shows that the image in camera link interface is fine and the SRIO transmission is successful.

Date Published: 17 September 2018
PDF: 7 pages
Proc. SPIE 10752, Applications of Digital Image Processing XLI, 1075226 (17 September 2018); doi: 10.1117/12.2320145

Published in SPIE Proceedings Vol. 10752:
Applications of Digital Image Processing XLI
Andrew G. Tescher, Editor(s)