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Proceedings Paper

FPGA implementation of full parallel LDPC encoder
Author(s): Zhaohui Wang; Xin Hao; Yujiao Zhao
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Paper Abstract

This paper gives a detailed introduction to the FPGA implementation of Full Parallel Low-Density ParityCheck(LDPC) Encoder, which is designed base on Richardson-Urbanke Algorithm with a code length 4096, code rate 4/5 on CCSDS standard. The proposed design use LUTs to solve matrix multiplication with low-complexity, the encode result can output in 4 clocks, the speed of the encoder can be higher than 6.4 Gbps, and the resource utilization is acceptable.

Paper Details

Date Published: 20 February 2018
PDF: 6 pages
Proc. SPIE 10697, Fourth Seminar on Novel Optoelectronic Detection Technology and Application, 1069751 (20 February 2018); doi: 10.1117/12.2307062
Show Author Affiliations
Zhaohui Wang, China Academy of Engineering Physics (China)
Xin Hao, China Academy of Engineering Physics (China)
Yujiao Zhao, China Academy of Engineering Physics (China)


Published in SPIE Proceedings Vol. 10697:
Fourth Seminar on Novel Optoelectronic Detection Technology and Application
Weiqi Jin; Ye Li, Editor(s)

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