Share Email Print

Proceedings Paper

Pin routability and pin access analysis on standard cells for layout optimization
Author(s): Jian Chen; Jun Wang; ChengYu Zhu; Wei Xu; Shuai Li; Eason Lin; Odie Ou; Ya-Chieh Lai; Shengrui Qu
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

At advanced process nodes, especially at sub-28nm technology, pin accessibility and routability of standard cells has become one of the most challenging design issues due to the limited router tracks and the increased pin density. If this issue can’t be found and resolved during the cell design stage, the pin access problem will be very difficult to be fixed in implementation stage and will make the low efficiency for routing.

In this paper, we will introduce a holistic approach for the pin accessibility scoring and routability analysis. For accessibility, the systematic calculator which assigns score for each pin will search the available access points, consider the surrounded router layers, basic design rule and allowed via geometry. Based on the score, the “bad” pins can be found and modified. On pin routability analysis, critical pin points (placing via on this point would lead to failed via insertion) will be searched out for either layout optimization guide or set as OBS for via insertion blocking. By using this pin routability and pin access analysis flow, we are able to improve the library quality and performance.

Paper Details

Date Published: 20 March 2018
PDF: 9 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880D (20 March 2018); doi: 10.1117/12.2297290
Show Author Affiliations
Jian Chen, Semiconductor Manufacturing International Corp. (China)
Jun Wang, Semiconductor Manufacturing International Corp. (China)
ChengYu Zhu, Semiconductor Manufacturing International Corp. (China)
Wei Xu, Cadence Design Systems, Inc. (United States)
Shuai Li, Cadence Design Systems, Inc. (United States)
Eason Lin, Cadence Design Systems, Inc. (United States)
Odie Ou, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Shengrui Qu, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top