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Proceedings Paper

Track height reduction for standard-cell in below 5nm node: how low can you go?
Author(s): S.M. Yasser Sherazi; Jung Kyu Chae; P. Debacker; L. Matti; P. Raghavan; V. Gerousis; D. Verkest; A. Mocuta; R.H. Kim; A. Spessot; J. Ryckaert
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Paper Abstract

The targeted 5nm and below technology node at IMEC has been defined by poly pitch 42nm and metal pitch 21nm. Compared to the previous node the CPP [1] remains the same and only the metal pitch is scaled down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that may enable this advance technology node and will require scaling boosters as Design-Technology co-optimization (DTCO).

Paper Details

Date Published: 20 March 2018
PDF: 13 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058809 (20 March 2018); doi: 10.1117/12.2297191
Show Author Affiliations
S.M. Yasser Sherazi, IMEC (Belgium)
Jung Kyu Chae, IMEC (Belgium)
P. Debacker, IMEC (Belgium)
L. Matti, Cadence Design Systems, Inc. (United States)
Technische Univ. Braunschweig (Germany)
P. Raghavan, IMEC (Belgium)
V. Gerousis, Cadence Design Systems, Inc. (United States)
Technische Univ. Braunschweig (Germany)
D. Verkest, IMEC (Belgium)
A. Mocuta, IMEC (Belgium)
R.H. Kim, IMEC (Belgium)
A. Spessot, IMEC (Belgium)
J. Ryckaert, IMEC (Belgium)


Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

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