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Proceedings Paper

Patterning method impact on sub-36nm pitch interconnect variability
Author(s): Nicholas V. LiCausi; James C.-H. Chen; R. S. Smith; E. Todd Ryan
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Paper Abstract

As advanced semiconductor technologies continue to shrink, there is a continued need for interconnect performance and variability to keep pace. Traditional area scaling alone cannot control the increased process variation at advanced nodes. We examine the impact that patterning scheme has on the final interconnect resistance, capacitance and RC variability at sub-36nm pitches. Industry standard patterning schemes are evaluated using the Monte Carlo method. Single exposure (direct print), litho-etch-litho-etch, self-aligned double patterning and self-aligned quadruple patterning (SAQP) are considered. In the context of these patterning schemes, lithographic variation and spacer thickness uniformity (where applicable) are evaluated.

Paper Details

Date Published: 20 March 2018
PDF: 12 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058804 (20 March 2018); doi: 10.1117/12.2297117
Show Author Affiliations
Nicholas V. LiCausi, GLOBALFOUNDRIES Inc. (United States)
James C.-H. Chen, IBM Research (United States)
R. S. Smith, GLOBALFOUNDRIES Inc. (United States)
E. Todd Ryan, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

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