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Proceedings Paper

A portable pattern-based design technology co-optimization flow to reduce optical proximity correction run-time
Author(s): Yi-Chieh Chen; Tsung-Han Li; Hung-Yu Lin; Kao-Tun Chen; Chun-Sheng Wu; Ya-Chieh Lai; Philippe Hurat
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Paper Abstract

Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTCO) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation.

PB-DTCO flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTCO flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.

Paper Details

Date Published: 20 March 2018
PDF: 6 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058810 (20 March 2018); doi: 10.1117/12.2297077
Show Author Affiliations
Yi-Chieh Chen, Cadence Design Systems, Inc. (Taiwan)
Tsung-Han Li, Winbond Electronics Corp. (Taiwan)
Hung-Yu Lin, Cadence Design Systems, Inc. (Taiwan)
Kao-Tun Chen, Winbond Electronics Corp. (Taiwan)
Chun-Sheng Wu, Winbond Electronics Corp. (Taiwan)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

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