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Proceedings Paper

DTCO exploration for efficient standard cell power rails
Author(s): Bharani Chava; Julien Ryckaert; Luca Mattii; Syed Muhammad Yasser Sherazi; Peter Debacker; Alessio Spessot; Diederik Verkest
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Paper Abstract

Standard cell track height scaling has been identified as an option to provide significant area savings. A direct consequence of track height reduction is that the width of the power rails needs to be reduced to accommodate patterning constraints as well as leave sufficient tracks for routing. Narrower power rails are highly resistive, reducing the headroom near an operating cell due to IR drop, which is not acceptable. For example, a 20% performance loss is observed due to a 10% supply voltage drop. To worsen the situation of IR drop, a slowdown in CPP scaling and newer metallization options are making the power rail highly sensitive and its design choice is a widely debated topic in the industry. Therefore, we propose an approach to define the power rail specifications and some feasible technology solutions to solve the power grid bottleneck.

Paper Details

Date Published: 20 March 2018
PDF: 6 pages
Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880B (20 March 2018); doi: 10.1117/12.2293500
Show Author Affiliations
Bharani Chava, IMEC (Belgium)
Julien Ryckaert, IMEC (Belgium)
Luca Mattii, IMEC (Belgium)
Syed Muhammad Yasser Sherazi, IMEC (Belgium)
Peter Debacker, IMEC (Belgium)
Alessio Spessot, IMEC (Belgium)
Diederik Verkest, IMEC (Belgium)

Published in SPIE Proceedings Vol. 10588:
Design-Process-Technology Co-optimization for Manufacturability XII
Jason P. Cain, Editor(s)

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