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Proceedings Paper

Optoelectronic parallel computing system with reconfigurable optical interconnection
Author(s): Masatoshi Ishikawa
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Paper Abstract

System architectures for optoelectronic parallel computing system are reviewed and a massively parallel processing system with a reconfigurable optical interconnection among electronic general purpose processing elements (PE’s) is described as an example. If PE is so compact, more than 4,000 PE’s can be integrated into one chip for directly coupling with array type optical devices in parallel. The optical interconnection is constructed using a surface emitting laser diode array and a phase modulation type spatial light modulator on which optimized computer generated holograms are written. In this paper, the design concept of optoelectronic parallel computing systems and PE’s, configurations of experimental system, and algorithms for parallel optoelectronic computing system are shown.

Paper Details

Date Published: 30 January 1996
PDF: 20 pages
Proc. SPIE 10284, Optoelectronic Interconnects and Packaging: A Critical Review, 102840A (30 January 1996); doi: 10.1117/12.229284
Show Author Affiliations
Masatoshi Ishikawa, Univ. of Tokyo (Japan)

Published in SPIE Proceedings Vol. 10284:
Optoelectronic Interconnects and Packaging: A Critical Review
Ray T. Chen; Peter S. Guilfoyle, Editor(s)

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