Share Email Print
cover

Proceedings Paper

Challenges and solutions for high-volume testing of silicon photonics
Author(s): Robert Polster; Liang Yuan Dai; Michail Oikonomou; Qixiang Cheng; Sebastien Rumley; Keren Bergman
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The first generation of silicon photonic products is now commercially available. While silicon photonics possesses key economic advantages over classical photonic platforms, it has yet to become a commercial success because these advantages can be fully realized only when high-volume testing of silicon photonic devices is made possible. We discuss the costs, challenges, and solutions of photonic chip testing as reported in the recent research literature. We define and propose three underlying paradigms that should be considered when creating photonic test structures: Design for Fast Coupling, Design for Minimal Taps, and Design for Parallel Testing. We underline that a coherent test methodology must be established prior to the design of test structures, and demonstrate how an optimized methodology dramatically reduces the burden when designing for test, by reducing the needed complexity of test structures.

Paper Details

Date Published: 22 February 2018
PDF: 8 pages
Proc. SPIE 10537, Silicon Photonics XIII, 1053703 (22 February 2018); doi: 10.1117/12.2292235
Show Author Affiliations
Robert Polster, Columbia Univ. (United States)
Liang Yuan Dai, Columbia Univ. (United States)
Michail Oikonomou, Columbia Univ. (United States)
Qixiang Cheng, Columbia Univ. (United States)
Sebastien Rumley, Columbia Univ. (United States)
Keren Bergman, Columbia Univ. (United States)


Published in SPIE Proceedings Vol. 10537:
Silicon Photonics XIII
Graham T. Reed; Andrew P. Knights, Editor(s)

© SPIE. Terms of Use
Back to Top