Proceedings Paper
Encoding of chain outputs in FPGA-based Moore FSMs| Format | Member Price | Non-Member Price |
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Paper Abstract
A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The
method is based on replacement of the state register by a state counter. The specific of the proposed method is
that the counter content is incremented for unconditional and conditional transitions. An example of application
of proposed method is given.
Paper Details
Date Published: 7 August 2017
PDF: 9 pages
Proc. SPIE 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017, 104452N (7 August 2017); doi: 10.1117/12.2281060
Published in SPIE Proceedings Vol. 10445:
Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017
Ryszard S. Romaniuk; Maciej Linczuk, Editor(s)
PDF: 9 pages
Proc. SPIE 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017, 104452N (7 August 2017); doi: 10.1117/12.2281060
Show Author Affiliations
Alexander Barkalov, Univ. of Zielona Góra (Poland)
Larysa Titarenko, Univ. of Zielona Góra (Poland)
Larysa Titarenko, Univ. of Zielona Góra (Poland)
Jacek Bieganowski, Univ. of Zielona Góra (Poland)
Published in SPIE Proceedings Vol. 10445:
Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017
Ryszard S. Romaniuk; Maciej Linczuk, Editor(s)
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