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Proceedings Paper

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer
Author(s): Saptarshi Mandal; Anchal Agarwal; Elaheh Ahmadi; K. Mahadeva Bhat; Matthew A. Laurent; Stacia Keller; Srabanti Chowdhury
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Paper Abstract

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

Paper Details

Date Published: 23 August 2017
PDF: 7 pages
Proc. SPIE 10381, Wide Bandgap Power Devices and Applications II, 1038108 (23 August 2017);
Show Author Affiliations
Saptarshi Mandal, Univ. of California, Davis (United States)
Anchal Agarwal, Univ. of California, Santa Barbara (United States)
Elaheh Ahmadi, Univ. of California, Santa Barbara (United States)
K. Mahadeva Bhat, Univ. of California, Davis (United States)
Matthew A. Laurent, Univ. of California, Davis (United States)
Stacia Keller, Univ. of California, Santa Barbara (United States)
Srabanti Chowdhury, Univ. of California, Davis (United States)


Published in SPIE Proceedings Vol. 10381:
Wide Bandgap Power Devices and Applications II
Mohammad Matin; Srabanti Chowdhury; Achyut K. Dutta, Editor(s)

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