In this paper, a 3D 1Gfps BSI image sensor is proposed, where 128 × 256 pixels are located in the top-tier chip and a 32 × 32 localized driver array in the bottom-tier chip. Pixels are designed with Multiple Collection Gates (MCG), which collects photons selectively with different collection gates being active at intervals of 1ns to achieve 1Gfps. For the drivers, a global PLL is designed, which consists of a ring oscillator with 6-stage current starved differential inverters, achieving a wide frequency tuning range from 40MHz to 360MHz (20ps rms jitter). The drivers are the replicas of the ring oscillator that operates within a PLL. Together with level shifters and XNOR gates, continuous 3.3V pulses are generated with desired pulse width, which is 1/12 of the PLL clock period. The driver array is activated by a START signal, which propagates through a highly balanced clock tree, to activate all the pixels at the same time with virtually negligible skew.

Date Published: 20 February 2017
PDF: 6 pages
Proc. SPIE 10328, Selected Papers from the 31st International Congress on High-Speed Imaging and Photonics, 1032807 (20 February 2017); doi: 10.1117/12.2268877

Published in SPIE Proceedings Vol. 10328:
Selected Papers from the 31st International Congress on High-Speed Imaging and Photonics
T. Goji Etoh; Hiroyuki Shiraga, Editor(s)