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Proceedings Paper

The application of advanced pulsed plasma in Fin etch loading improvement
Author(s): Fang-Yuan Xiao; Qiu-Hua Han; Hai-Yang Zhang
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Paper Abstract

Following Moore’s law, integrated circuit requires scaling gate length to 14nm and beyond. To enable such gate-length scaling, finFETs have widely replaced planar metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its special 3D structure could provide larger effective channel width and better short channel controllability. However, Fin critical dimension (CD) and profile variation between dense and ISO fin in a conventional etch process can introduce additional device degradation. Therefore, rigorous process loading control in reactive ion etch (RIE) becomes more critical. This paper mainly focused on self-aligned double patterning mandrel etch and fin etch by using advanced pulsed plasma to deliver a well-loading fin.

Paper Details

Date Published: 21 March 2017
PDF: 4 pages
Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 101490Z (21 March 2017); doi: 10.1117/12.2266539
Show Author Affiliations
Fang-Yuan Xiao, Semiconductor Manufacturing International Corp. (China)
Qiu-Hua Han, Semiconductor Manufacturing International Corp. (China)
Hai-Yang Zhang, Semiconductor Manufacturing International Corp. (China)

Published in SPIE Proceedings Vol. 10149:
Advanced Etch Technology for Nanopatterning VI
Sebastian U. Engelmann, Editor(s)

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