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Proceedings Paper

Equalizing Si photodetectors fabricated in standard CMOS processes
Author(s): E. Guerrero; J. Aguirre; C. Sánchez-Azqueta; G. Royo; C. Gimeno; S. Celma
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Paper Abstract

This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

Paper Details

Date Published: 30 May 2017
PDF: 7 pages
Proc. SPIE 10249, Integrated Photonics: Materials, Devices, and Applications IV, 102490N (30 May 2017); doi: 10.1117/12.2264603
Show Author Affiliations
E. Guerrero, Univ. de Zaragoza (Spain)
J. Aguirre, Univ. de Zaragoza (Spain)
C. Sánchez-Azqueta, Univ. de Zaragoza (Spain)
G. Royo, Univ. de Zaragoza (Spain)
C. Gimeno, Univ. Catholique de Louvain (Belgium)
S. Celma, Univ. de Zaragoza (Spain)

Published in SPIE Proceedings Vol. 10249:
Integrated Photonics: Materials, Devices, and Applications IV
Jean-Marc Fédéli; Laurent Vivien, Editor(s)

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