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Proceedings Paper

In-design and signoff lithography physical analysis for 7/5nm (Erratum)
Author(s): Cyrus Tabery; Jun Ye; Yi Zou; Vincent Arnoux; Praveen Raghavan; Ryoung-han Kim; Michel Côté; Luca Mattii; Ya-Chieh Lai; Philippe Hurat
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Paper Abstract

Publisher’s Note: This paper, originally published on 30-March, 2017, was replaced with a corrected/revised version on 6-April, 2017. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

At advanced nodes, definition of design rules and process options must be tightly optimized to deliver the best tradeoff performance, power, area and manufacturability. However, implementation platforms don’t typically have access to process information and process teams don’t have design knowledge, and optimization loops required for Design-Technology-Co-Optimization (DTCO) are either impossible or at best long and expensive for fabless design house.

Joining forces, ASML, IMEC and Cadence Design Systems developed an In-design and signoff lithography physical analysis well suited for 7/5nm and below. The Tachyon OPC+ engine used by IMEC 7/5nm process has been integrated in Cadence Litho Physical Analyzer (LPA) to perform lithography checks using the foundry process models, recipes, and hotspot detectors. This flow leverages existing LPA infrastructure for both custom and digital design platforms, as well as standalone signoff.

Depending upon the end application, LPA could be launched either from place & route or custom layout or standalone. LPA processes first the design database to identify hierarchy, decompose the layout for coloring and apply pattern matching to identify location requiring simulation. The layout is then passed to the Tachyon OPC tool to perform optical process correction and model-based litho verification that is validated on Silicon. The hotspots and contours are processed by LPA for generation of hotspot marker and fixing guidelines and provide all this information to the design environment.

The flow has been developed and demonstrated to work on IMEC 7nm, and can be ported to smaller or larger technologies. The paper will present the result of this In-design and signoff lithography physical analysis flow, how DTCO and design teams can add manufacturability to PPA.

Paper Details

Date Published: 30 March 2017
PDF: 6 pages
Proc. SPIE 10147, Optical Microlithography XXX, 1014705 (30 March 2017); doi: 10.1117/12.2263861
Show Author Affiliations
Cyrus Tabery, ASML US, Inc. (United States)
Jun Ye, ASML US, Inc. (United States)
Yi Zou, ASML US, Inc. (United States)
Vincent Arnoux, ASML US, Inc. (United States)
Praveen Raghavan, IMEC (Belgium)
Ryoung-han Kim, IMEC (Belgium)
Michel Côté, Cadence Design Systems, Inc. (United States)
Luca Mattii, Cadence Design Systems, Inc. (Belgium)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 10147:
Optical Microlithography XXX
Andreas Erdmann; Jongwook Kye, Editor(s)

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