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Proceedings Paper

Silicon pixel detector prototyping in SOI CMOS technology
Author(s): Roma Dasgupta; Szymon Bugiel; Marek Idzik; Piotr Kapusta; Wojciech Kucewicz; Michal Turala
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Paper Abstract

The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

Paper Details

Date Published: 22 December 2016
PDF: 6 pages
Proc. SPIE 10175, Electron Technology Conference 2016, 1017505 (22 December 2016); doi: 10.1117/12.2261485
Show Author Affiliations
Roma Dasgupta, AGH Univ. of Science and Technology (Poland)
Szymon Bugiel, AGH Univ. of Science and Technology (Poland)
Marek Idzik, AGH Univ. of Science and Technology (Poland)
Piotr Kapusta, Institute of Nuclear Physics (Poland)
Wojciech Kucewicz, AGH Univ. of Science and Technology (Poland)
Michal Turala, Institute of Nuclear Physics (Poland)

Published in SPIE Proceedings Vol. 10175:
Electron Technology Conference 2016
Barbara Swatowska; Wojciech Maziarz; Tadeusz Pisarkiewicz; Wojciech Kucewicz, Editor(s)

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