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Proceedings Paper

An acceleration framework for synthetic aperture radar algorithms
Author(s): Youngsoo Kim; Clay S. Gloster; Winser E. Alexander
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Paper Abstract

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.

Paper Details

Date Published: 28 April 2017
PDF: 10 pages
Proc. SPIE 10201, Algorithms for Synthetic Aperture Radar Imagery XXIV, 102010F (28 April 2017); doi: 10.1117/12.2261397
Show Author Affiliations
Youngsoo Kim, San Jose State Univ. (United States)
Clay S. Gloster, North Carolina A&T State Univ. (United States)
Winser E. Alexander, North Carolina State Univ. (United States)

Published in SPIE Proceedings Vol. 10201:
Algorithms for Synthetic Aperture Radar Imagery XXIV
Edmund Zelnio; Frederick D. Garber, Editor(s)

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