Transistor scaling has transitioned from wavelength scaling to multi-patterning techniques, due to the resolution limits of immersion of immersion lithography. Deposition and etch have enabled scaling in the by means of SADP and SAQP. Spacer based patterning enables extremely small linewidths, sufficient for several future generations of transistors. However, aligning layers in Z-direction, as well as aligning cut and via patterning layers, is becoming a road-block due to global and local feature variation and fidelity. This presentation will highlight the impact of deposition and etch on this feature alignment (EPE) and illustrate potential paths toward lowering EPE using material engineering.

Date Published: 27 April 2017
PDF: 1 pages
Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 1014905 (27 April 2017); doi: 10.1117/12.2261107

Published in SPIE Proceedings Vol. 10149:
Advanced Etch Technology for Nanopatterning VI
Sebastian U. Engelmann, Editor(s)