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Proceedings Paper

Bipolar transistor in VESTIC technology: prototype
Author(s): Piotr Mierzwiński; Wiesław Kuźmicz; Krzysztof Domański; Daniel Tomaszewski; Grzegorz Głuszko
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Paper Abstract

VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.

Paper Details

Date Published: 22 December 2016
PDF: 9 pages
Proc. SPIE 10175, Electron Technology Conference 2016, 101750E (22 December 2016); doi: 10.1117/12.2260787
Show Author Affiliations
Piotr Mierzwiński, Warsaw Univ. of Technology (Poland)
Wiesław Kuźmicz, Warsaw Univ. of Technology (Poland)
Krzysztof Domański, Institute of Electron Technology (Poland)
Daniel Tomaszewski, Institute of Electron Technology (Poland)
Grzegorz Głuszko, Institute of Electron Technology (Poland)

Published in SPIE Proceedings Vol. 10175:
Electron Technology Conference 2016
Barbara Swatowska; Wojciech Maziarz; Tadeusz Pisarkiewicz; Wojciech Kucewicz, Editor(s)

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