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Proceedings Paper

High-throughput electrical characterization for robust overlay lithography control
Author(s): Devender Devender; Xumin Shen; Mark Duggan; Sunil Singh; Jonathan Rullan; Jae Choo; Sohan Mehta; Teck Jung Tang; Sean Reidy; Jonathan Holt; Hyung Woo Kim; Robert Fox; D. K. Sohn
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Paper Abstract

Realizing sensitive, high throughput and robust overlay measurement is a challenge in current 14nm and advanced upcoming nodes with transition to 300mm and upcoming 450mm semiconductor manufacturing, where slight deviation in overlay has significant impact on reliability and yield1). Exponentially increasing number of critical masks in multi-patterning lithoetch, litho-etch (LELE) and subsequent LELELE semiconductor processes require even tighter overlay specification2). Here, we discuss limitations of current image- and diffraction- based overlay measurement techniques to meet these stringent processing requirements due to sensitivity, throughput and low contrast3). We demonstrate a new electrical measurement based technique where resistance is measured for a macro with intentional misalignment between two layers. Overlay is quantified by a parabolic fitting model to resistance where minima and inflection points are extracted to characterize overlay control and process window, respectively. Analyses using transmission electron microscopy show good correlation between actual overlay performance and overlay obtained from fitting. Additionally, excellent correlation of overlay from electrical measurements to existing image- and diffraction- based techniques is found. We also discuss challenges of integrating electrical measurement based approach in semiconductor manufacturing from Back End of Line (BEOL) perspective. Our findings open up a new pathway for accessing simultaneous overlay as well as process window and margins from a robust, high throughput and electrical measurement approach.

Paper Details

Date Published: 28 March 2017
PDF: 11 pages
Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 101450K (28 March 2017); doi: 10.1117/12.2260707
Show Author Affiliations
Devender Devender, GLOBALFOUNDRIES Inc. (United States)
Xumin Shen, PDF Solutions, Inc. (United States)
Mark Duggan, GLOBALFOUNDRIES Inc. (United States)
Sunil Singh, GLOBALFOUNDRIES Inc. (United States)
Jonathan Rullan, GLOBALFOUNDRIES Inc. (United States)
Jae Choo, GLOBALFOUNDRIES Inc. (United States)
Sohan Mehta, GLOBALFOUNDRIES Inc. (United States)
Teck Jung Tang, GLOBALFOUNDRIES Inc. (United States)
Sean Reidy, GLOBALFOUNDRIES Inc. (United States)
Jonathan Holt, PDF Solutions, Inc. (United States)
Hyung Woo Kim, GLOBALFOUNDRIES Inc. (United States)
Robert Fox, GLOBALFOUNDRIES Inc. (United States)
D. K. Sohn, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 10145:
Metrology, Inspection, and Process Control for Microlithography XXXI
Martha I. Sanchez, Editor(s)

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