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Electrical study of DSA shrink process and CD rectification effect at sub-60nm using EUV test vehicle
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Paper Abstract

In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.

Paper Details

Date Published: 13 April 2017
PDF: 8 pages
Proc. SPIE 10146, Advances in Patterning Materials and Processes XXXIV, 101460Q (13 April 2017); doi: 10.1117/12.2260454
Show Author Affiliations
Cheng Chi, IBM Corp. (United States)
Chi-Chun Liu, IBM Corp. (United States)
Luciana Meli, IBM Corp. (United States)
Jing Guo, IBM Corp. (United States)
Doni Parnell, TEL Technology Ctr., America, LLC (United States)
Yann Mignot, IBM Corp. (United States)
Kristin Schmidt, IBM Corp. (United States)
Martha Sanchez, IBM Corp. (United States)
Richard Farrell, TEL Technology Ctr., America, LLC (United States)
Lovejeet Singh, JSR Micro, Inc. (United States)
Tsuyoshi Furukawa, JSR Micro, Inc. (United States)
Kafai Lai, IBM Corp. (United States)
Yongan Xu, IBM Corp. (United States)
Daniel Sanders, IBM Corp. (United States)
David Hetzer, TEL Technology Ctr., America, LLC (United States)
Andrew Metz, TEL Technology Ctr., America, LLC (United States)
Sean Burns, IBM Corp. (United States)
Nelson Felix, IBM Corp. (United States)
John Arnold, IBM Corp. (United States)
Daniel Corliss, IBM Corp. (United States)

Published in SPIE Proceedings Vol. 10146:
Advances in Patterning Materials and Processes XXXIV
Christoph K. Hohle, Editor(s)

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