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Proceedings Paper

Process weakness assessment by profiling all incoming design components
Author(s): Linda Zhuang; MengFeng Cai; Annie Zhu; Yifan Zhang; Jason Sweis; Ya-Chieh Lai
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Paper Abstract

Foundries normally receive a large number of designs from different customers every day. It is desired to automatically profile each incoming design to quantify certain metrics like 1) the number of polygons per GDS layers 2) what kind of electrical components the design contains 3) what the dimensions of each electrical component are 4) how frequently any size of components have been used and their physical locations.

This paper will present a novel method of how to generate a complete profile of components for any particular design. The component checking flow need to be completed within hours so it will have very little impact on the tape-out time. A pre-layer checking method is also run to group commonly used layers for different electrical components and then employ different layout profiling flows. The foundry does this design chip analysis in order to find potentially weak devices due to their size or special size requirements for particular electrical components. The foundry can then take pre-emptive action to avoid yield loss or make an unnecessary mask for new incoming products before fab processing starts.

Paper Details

Date Published: 30 March 2017
PDF: 5 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014819 (30 March 2017); doi: 10.1117/12.2260311
Show Author Affiliations
Linda Zhuang, Semiconductor Manufacturing International Corp. (China)
MengFeng Cai, Semiconductor Manufacturing International Corp. (China)
Annie Zhu, Semiconductor Manufacturing International Corp. (China)
Yifan Zhang, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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