Proceedings Paper
Transforming information from silicon testing and design characterization into numerical data sets for yield learning| Format | Member Price | Non-Member Price |
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Paper Abstract
Silicon testing results are regularly collected for a particular lot of wafers to study yield loss from
test result diagnostics. Product engineers will analyze the diagnostic results and perform a number
of physical failure analyses to detect systematic defects which cause yield loss for these sets of
wafers in order to feedback the information to process engineers for process improvements. Most
of time, the systematic defects that are detected are major issues or just one of the causes for the
overall yield loss.
This paper will present a working flow for using design analysis techniques combined with diagnostic methods to systematically transform silicon testing information into physical layout information. A new set of the testing results are received from a new lot of wafers for the same product. We can then correlate all the diagnostic results from different periods of time to check which blocks or nets have been highlighted or stop occurring on the failure reports in order to monitor process changes which impact the yield. The design characteristic analysis flow is also implemented to find 1) the block connections on a design that have failed electrical test or 2) frequently used cells that been highlighted multiple times.
This paper will present a working flow for using design analysis techniques combined with diagnostic methods to systematically transform silicon testing information into physical layout information. A new set of the testing results are received from a new lot of wafers for the same product. We can then correlate all the diagnostic results from different periods of time to check which blocks or nets have been highlighted or stop occurring on the failure reports in order to monitor process changes which impact the yield. The design characteristic analysis flow is also implemented to find 1) the block connections on a design that have failed electrical test or 2) frequently used cells that been highlighted multiple times.
Paper Details
Date Published: 30 March 2017
PDF: 5 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480W (30 March 2017); doi: 10.1117/12.2259950
Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)
PDF: 5 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480W (30 March 2017); doi: 10.1117/12.2259950
Show Author Affiliations
Thomas Yang, Semiconductor Manufacturing International Corp. (China)
Yang Shen, Semiconductor Manufacturing International Corp. (China)
Yifan Zhang, Cadence Design Systems, Inc. (United States)
Yang Shen, Semiconductor Manufacturing International Corp. (China)
Yifan Zhang, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)
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