Share Email Print

Proceedings Paper

Electrical failure debug using interlayer profiling method
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

It is very well known that as technology nodes move to smaller sizes, the number of design rules increases while design structures become more regular and the process manufacturing steps have increased as well. Normal inspection tools can only monitor hard failures on a single layer. For electrical failures that happen due to inter layers misalignments, we can only detect them through testing.

This paper will present a working flow for using pattern analysis interlayer profiling techniques to turn multiple layer physical info into group linked parameter values. Using this data analysis flow combined with an electrical model allows us to find critical regions on a layout for yield learning.

Paper Details

Date Published: 30 March 2017
PDF: 6 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101481D (30 March 2017); doi: 10.1117/12.2259944
Show Author Affiliations
Thomas Yang, Semiconductor Manufacturing International Corp. (China)
Yang Shen, Semiconductor Manufacturing International Corp. (China)
Yifan Zhang, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?