
Proceedings Paper
Imbalance aware lithography hotspot detection: a deep learning approachFormat | Member Price | Non-Member Price |
---|---|---|
$17.00 | $21.00 |
Paper Abstract
With the advancement of VLSI technology nodes, light diffraction caused lithographic hotspots have become a serious problem affecting manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with extreme scaling of transistor feature size and more and more complicated layout patterns, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. In this paper, we present a deep convolutional neural network (CNN) targeting representative feature learning in lithography hotspot detection. We carefully analyze impact and effectiveness of different CNN hyper-parameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always minorities in VLSI mask design, the training data set is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from high false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply minority upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves highly comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.
Paper Details
Date Published: 28 March 2017
PDF: 16 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014807 (28 March 2017); doi: 10.1117/12.2258374
Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)
PDF: 16 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014807 (28 March 2017); doi: 10.1117/12.2258374
Show Author Affiliations
Haoyu Yang, The Chinese Univ. of Hong Kong (Hong Kong, China)
Luyang Luo, The Chinese Univ. of Hong Kong (Hong Kong, China)
Jing Su, ASML Brion (United States)
Luyang Luo, The Chinese Univ. of Hong Kong (Hong Kong, China)
Jing Su, ASML Brion (United States)
Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)
© SPIE. Terms of Use
