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Proceedings Paper

RLT uniformity improvement utilizing multi-scale NIL process simulation
Author(s): Sachiko Kobayashi; Ryoichi Inanami; Hirotaka Tsuda; Kazuhiro Washida; Motofumi Komori; Kyoji Yamashita; Ji-Young Im; Takuya Kono; Shimon Maeda
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Paper Abstract

Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. To apply smaller pattern size device, layout dependent hotspots becomes a significant issue, so design for manufacturing (DFM) flow considering imprint process has to be prepared. In this paper, focused on fine resist spread, RLT (Residual Layer Thickness) uniformity improvement utilizing simulation is demonstrated and resist drop compliance check flow is proposed

Paper Details

Date Published: 31 March 2017
PDF: 7 pages
Proc. SPIE 10144, Emerging Patterning Technologies, 101440X (31 March 2017); doi: 10.1117/12.2258172
Show Author Affiliations
Sachiko Kobayashi, Toshiba Corp. (Japan)
Ryoichi Inanami, Toshiba Corp. (Japan)
Hirotaka Tsuda, Toshiba Corp. (Japan)
Kazuhiro Washida, Toshiba Corp. (Japan)
Motofumi Komori, Toshiba Corp. (Japan)
Kyoji Yamashita, Toshiba Corp. (Japan)
Ji-Young Im, SK Hynix, Inc (Korea, Republic of)
Takuya Kono, Toshiba Corp. (Japan)
Shimon Maeda, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 10144:
Emerging Patterning Technologies
Christopher Bencher, Editor(s)

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