Share Email Print

Proceedings Paper

Roughness and uniformity improvements on self-aligned quadruple patterning technique for 10nm node and beyond by wafer stress engineering
Author(s): Eric Liu; Akiteru Ko; David O'Meara; Nihar Mohanty; Elliott Franke; Karthik Pillai; Peter Biolsi
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Dimension shrinkage has been a major driving force in the development of integrated circuit processing over a number of decades. The Self-Aligned Quadruple Patterning (SAQP) technique is widely adapted for sub-10nm node in order to achieve the desired feature dimensions. This technique provides theoretical feasibility of multiple pitch-halving from 193nm immersion lithography by using various pattern transferring steps. The major concept of this approach is to a create spacer defined self-aligned pattern by using single lithography print. By repeating the process steps, double, quadruple, or octuple are possible to be achieved theoretically. In these small architectures, line roughness control becomes extremely important since it may contribute to a significant portion of process and device performance variations. In addition, the complexity of SAQP in terms of processing flow makes the roughness improvement indirective and ineffective. It is necessary to discover a new approach in order to improve the roughness in the current SAQP technique.

In this presentation, we demonstrate a novel method to improve line roughness performances on 30nm pitch SAQP flow. We discover that the line roughness performance is strongly related to stress management. By selecting different stress level of film to be deposited onto the substrate, we can manipulate the roughness performance in line and space patterns. In addition, the impact of curvature change by applied film stress to SAQP line roughness performance is also studied. No significant correlation is found between wafer curvature and line roughness performance. We will discuss in details the step-by-step physical performances for each processing step in terms of critical dimension (CD)/ critical dimension uniformity (CDU)/line width roughness (LWR)/line edge roughness (LER). Finally, we summarize the process needed to reach the full wafer performance targets of LWR/LER in 1.07nm/1.13nm on 30nm pitch line and space pattern.

Paper Details

Date Published: 9 May 2017
PDF: 10 pages
Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 101490W (9 May 2017); doi: 10.1117/12.2258097
Show Author Affiliations
Eric Liu, TEL Technology Ctr., America, LLC (United States)
Akiteru Ko, TEL Technology Ctr., America, LLC (United States)
David O'Meara, TEL Technology Ctr., America, LLC (United States)
Nihar Mohanty, TEL Technology Ctr., America, LLC (United States)
Elliott Franke, TEL Technology Ctr., America, LLC (United States)
Karthik Pillai, TEL Technology Ctr., America, LLC (United States)
Peter Biolsi, TEL Technology Ctr., America, LLC (United States)

Published in SPIE Proceedings Vol. 10149:
Advanced Etch Technology for Nanopatterning VI
Sebastian U. Engelmann, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?