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Proceedings Paper

Selection of airgap layers for circuit timing optimization
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Paper Abstract

Airgap refers to a void formed in place of some inter metal dielectric (IMD). It brings about the reduction in coupling capacitance, which may contribute to improvement in circuit performance. We introduce two problems in this context. First is to choose the layers, where airgap should be applied, in such a way that total negative slack (TNS) is minimized for a given circuit. This has been motivated by the fact that best choice of airgap layers is different for different circuits. An algorithm is proposed to solve the problem, and is assessed against a naive approach in which airgap layers are simply fixed; additional 8% TNS reduction, on average of a few test circuits, is demonstrated. In the second problem, some wires of critical paths that are on non-airgap layers are reassigned to airgap layers such that TNS is further reduced; additional 3 to 14% of TNS reduction is observed.

Paper Details

Date Published: 28 March 2017
PDF: 8 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480O (28 March 2017); doi: 10.1117/12.2258034
Show Author Affiliations
Daijoon Hyun, KAIST (Korea, Republic of)
SAMSUNG Electronics Co., Inc. (Korea, Republic of)
Youngsoo Shin, KAIST (Korea, Republic of)

Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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