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Proceedings Paper

Co-optimization of lithographic and patterning processes for improved EPE performance
Author(s): Mark J. Maslow; Vadim Timoshkov; Ton Kiers; Tae Kwon Jee; Peter de Loijer; Shinya Morikita; Marc Demand; Andrew W. Metz; Soichiro Okada; Kaushik A. Kumar; Serge Biesemans; Hidetami Yaegashi; Paolo Di Lorenzo; Joost P. Bekaert; Ming Mao; Christophe Beral; Stephane Larivière
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Paper Abstract

Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.

To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.

Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

Paper Details

Date Published: 21 March 2017
PDF: 16 pages
Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 101490N (21 March 2017); doi: 10.1117/12.2257979
Show Author Affiliations
Mark J. Maslow, ASML Netherlands B.V. (Netherlands)
Vadim Timoshkov, ASML Netherlands B.V. (Netherlands)
Ton Kiers, ASML Netherlands B.V. (Netherlands)
Tae Kwon Jee, ASML Netherlands B.V. (Netherlands)
Peter de Loijer, ASML Netherlands B.V. (Netherlands)
Shinya Morikita, Tokyo Electron Ltd. (Japan)
Marc Demand, Tokyo Electron Ltd. (Japan)
Andrew W. Metz, Tokyo Electron Ltd. (Japan)
Soichiro Okada, Tokyo Electron Ltd. (Japan)
Kaushik A. Kumar, Tokyo Electron Ltd. (Japan)
Serge Biesemans, Tokyo Electron Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)
Paolo Di Lorenzo, IMEC (Belgium)
Joost P. Bekaert, IMEC (Belgium)
Ming Mao, IMEC (Belgium)
Christophe Beral, IMEC (Belgium)
Stephane Larivière, IMEC (Belgium)

Published in SPIE Proceedings Vol. 10149:
Advanced Etch Technology for Nanopatterning VI
Sebastian U. Engelmann, Editor(s)

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