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Proceedings Paper

Low track height standard-cells enable high-placement density and low-BEOL cost (Conference Presentation)
Author(s): Peter Debacker; Luca Matti; Syed M. Y. Sherazi; Rogier Baert; Vassilios Gerousis; Claire Nauts; Praveen Raghavan; Julien Ryckaert; Ryoung-Han Kim; Diederik Verkest

Paper Abstract

Making standards cells smaller by lowering the cell height from 7.5 tracks to 6 tracks for the same set of ground rules is an efficient way to reduce area for high density digital IP blocks without increasing wafer cost. Denser cells however also imply a higher pin density and possible more routing congestion because of that. In Place and Route phase, this limits the cell density (a.k.a. utilization) that can be reached without design rule violations. This study shows that 6-track cells (192nm high) and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Standard cells have been created for 7.5T and 6T cells in N5 technology (poly pitch 42nm, metal pitch 32nm). The cells use a first horizontal routing layer (Mint) and vertical M1 for 1D intra-cell routing as much as possible. Place and route was performed on an opencores LDPC decoder. Various cell architectures and place and route optimizations are used to scale down the cell area and improve density. Most are not process optimizations, but optimized cell architectures and routing methods: • Open M1: M1 is removed as much as possible. This allows the router to use M1 for inter-cell routing in dense areas. • Routing in Mint: With open M1 the router can also use Mint to extend pins to access nearby free M1 tracks in congested areas. • Outbound rail: The 7.5T cells have inbound VDD/VSS rails in Mint for easy supply tapping. Moving the Mint rail outbound and shared between cells is required to enable lower track height cells. • Vertical Power distribution network (PDN): in 6T cells too many horizontal tracks would be consumed by the wide M2 rail. Mint is used instead combined with a vertical PDN in M1. • Self-Aligned Gate Contact allows to contact the gate on top of active fins. Any Mint track then can contact a gate, reducing cell area considerably. • Partially landing Mint Via trench: In 6T cells, a continuous Via trench underneath the Mint rail is used. This via partially lands on M0A to relax tip-to-tip requirements. • Relaxed M2 pitch: When pin access is handled in Mint and M1, this allows for a relaxed M2 pitch (48nm) with cheaper double patterning. To avoid horizontal routing layer congestion with the smaller cells, the 6T cells depend on the vertical PDN and open M1 to improve routability and pin access. Already in 7.5T cells, open M1 and vertical PDN help to improve routable utilization from 50% with closed M1 to 85% maximum. Moving to 6T cells, the combination of reduced cell area and high 85% utilization of result in a 60% area reduction vs the original 7.5T cells. We have shown that combining 6-track cells and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Open M1 and vertical PDN are main area boosters for any cell architecture, boosting utilization from 50% to 85% already for the 7.5T cells.

Paper Details

Date Published: 3 May 2017
PDF: 1 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014803 (3 May 2017); doi: 10.1117/12.2257961
Show Author Affiliations
Peter Debacker, IMEC VZW (Belgium)
Luca Matti, Cadence Design Systems, Inc. (United States)
Technische Univ. Braunschweig (Germany)
Syed M. Y. Sherazi, IMEC VZW (Belgium)
Rogier Baert, IMEC VZW (Belgium)
Vassilios Gerousis, Cadence Design Systems, Inc. (United States)
Claire Nauts, Cadence Design Systems, Inc. (United States)
Praveen Raghavan, IMEC VZW (Belgium)
Julien Ryckaert, IMEC VZW (Belgium)
Ryoung-Han Kim, IMEC VZW (Belgium)
Diederik Verkest, IMEC VZW (Belgium)

Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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