imec’s DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of 42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell design, integration and patterning specification are discussed.

Date Published: 26 April 2017
PDF: 8 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480V (26 April 2017); doi: 10.1117/12.2257885

Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)