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Proceedings Paper

Wafer hot spot identification through advanced photomask characterization techniques: part 2
Author(s): Yohan Choi; Michael Green; Young Cho; Young Ham; Howard Lin; Andy Lan; Richer Yang; Mike Lung
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Paper Abstract

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

Paper Details

Date Published: 28 March 2017
PDF: 8 pages
Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480L (28 March 2017); doi: 10.1117/12.2257676
Show Author Affiliations
Yohan Choi, Photronics, Inc. (United States)
Michael Green, Photronics, Inc. (United States)
Young Cho, Photronics, Inc. (United States)
Young Ham, Photronics, Inc. (United States)
Howard Lin, Inotera Memories Inc. (Taiwan)
Andy Lan, Inotera Memories Inc. (Taiwan)
Richer Yang, Inotera Memories Inc. (Taiwan)
Mike Lung, Inotera Memories Inc. (Taiwan)

Published in SPIE Proceedings Vol. 10148:
Design-Process-Technology Co-optimization for Manufacturability XI
Luigi Capodieci; Jason P. Cain, Editor(s)

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