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Proceedings Paper

8-inch GaN on Si-based wafer-level chip-scale package (Conference Presentation)
Author(s): Jun-Youn Kim

Paper Abstract

To reduce the $/lm for GaN-based LEDs, most LED makers are adopting flip-chip based Chip Scale Packaging (CSP) technology. However, it is difficult to realize true wafer-level (WL) CSP technology with conventional sapphire substrates caused by “blue light leak” issue. On the other hand, thin-film flip-chip technology practically eliminates blue light leak and allows a simpler process of phosphor coating and dicing. To maximize the advantages of WL-CSP, large diameter process is necessary for it to be cost effective. In this sense, 8 inch Si wafer is the best candidate. GaN-on-Si based LEDs, however, have seen little growth in the lighting market due to several issues that hamper the efficiency and reliability related to the quality of GaN films grown on Si. However, we have overcome all drawbacks including yield, device reliability and LM-80 by proprietary stress-managed buffer and optimized LED epitaxial structure. In addition to the comparable efficiency and reliability performance, we discovered several other advantages of using 8 inch Si substrates such as the wavelength uniformity, low thermal droop and low compressive strain of MQW. Wafer-level chip scale package (WL-CSP) on silicon substrates has its own set of advantages such as relatively easier to texture the GaN or phosphor surface at the wafer level to maximize photon extraction efficiency and multi-layer phosphor coating to further push the efficiency upwards.

Paper Details

Date Published: 19 April 2017
PDF: 1 pages
Proc. SPIE 10104, Gallium Nitride Materials and Devices XII, 101041Z (19 April 2017); doi: 10.1117/12.2252465
Show Author Affiliations
Jun-Youn Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)

Published in SPIE Proceedings Vol. 10104:
Gallium Nitride Materials and Devices XII
Jen-Inn Chyi; Hiroshi Fujioka; Hadis Morkoç; Yasushi Nanishi; Ulrich T. Schwarz; Jong-In Shim, Editor(s)

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