Share Email Print

Proceedings Paper

CMOS-compatible optical AND, OR, and XOR gates using voltage-induced free-carrier dispersion and stimulated Raman scattering
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

We present a theoretical model for two high-throughput optical logic methodologies, using voltage-induced free-carrier dispersion and stimulated Raman scattering based Zeno switching. Increased computational throughput is achieved by accessing higher switching speeds, optimizing the use of space, and by using multiple wavelengths for parallel processing. The condition of CMOS compatibility is maintained to take advantage of the high-volume, low-cost manufacturing potential of the industry and to help lower each design's spatial footprint (enabled by the high refractive index contrast of silicon-on-insulator waveguides and resonators). Each design is made with the potential of higher-order operations in mind; for their use must not only stand alone, but must also have the ability to incorporate into future all-optical or optoelectronic computational devices.

Paper Details

Date Published: 20 February 2017
PDF: 7 pages
Proc. SPIE 10108, Silicon Photonics XII, 101080Q (20 February 2017); doi: 10.1117/12.2251616
Show Author Affiliations
Dusan Gostimirovic, Carleton Univ. (Canada)
Winnie N. Ye, Carleton Univ. (Canada)

Published in SPIE Proceedings Vol. 10108:
Silicon Photonics XII
Graham T. Reed; Andrew P. Knights, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?