In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today’s low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.

Date Published: 20 October 2016
PDF: 7 pages
Proc. SPIE 10032, 32nd European Mask and Lithography Conference, 100320D (20 October 2016); doi: 10.1117/12.2248325

Published in SPIE Proceedings Vol. 10032:
32nd European Mask and Lithography Conference
Uwe F.W. Behringer; Jo Finders, Editor(s)