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Proceedings Paper

Combining mask and OPC process verification for improved wafer patterning and yield
Author(s): Ayman Hamouda; Hesham Abdelghany
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Paper Abstract

As technology advances into deep submicron nodes, the mask manufacturing process accuracy become more important. Mask Process Correction (MPC) has been transitioning from Rules-Based Mask Process correction to Model-Based Mask Process Correction mode. MPC is a subsequent step to OPC, where additional perturbation is applied to the mask shapes to correct for the mask manufacturing process. Shifting towards full model-based MPC is driven mainly by the accuracy requirements in advanced technology nodes, both for DUV and EUV processes. In the current state-of-the-art MPC process, MPC is completely decoupled from OPC, where each of them assumes that the other is executing perfectly. However, this decoupling is not suitable anymore due to the limited tolerance in the mask CDU budget and the increased wafer CDU requirements required from OPC. It is becoming more important to reduce any systematic mask errors, especially where they matter the most. In this work, we present a new combined-verification methodology that allows testing the combined effect of mask process and lithography process together and judging the final wafer patterning quality. This has the potential to intercept risks due to superposition of OPC and MPC correction residual errors, and capturing and correcting such a previously hidden source of patterning degradation.

Paper Details

Date Published: 25 October 2016
PDF: 6 pages
Proc. SPIE 9985, Photomask Technology 2016, 99852A (25 October 2016); doi: 10.1117/12.2246563
Show Author Affiliations
Ayman Hamouda, GLOBALFOUNDRIES (United States)
Hesham Abdelghany, GLOBALFOUNDRIES (United States)

Published in SPIE Proceedings Vol. 9985:
Photomask Technology 2016
Bryan S. Kasprowicz; Peter D. Buck, Editor(s)

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