Proceedings Paper
Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations| Format | Member Price | Non-Member Price |
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Paper Abstract
The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.
Paper Details
Date Published: 12 October 2016
PDF: 5 pages
Proc. SPIE 9818, 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage, 98180L (12 October 2016); doi: 10.1117/12.2245306
Published in SPIE Proceedings Vol. 9818:
2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage
Fuxi Gan; Zhitang Song; Yang Wang, Editor(s)
PDF: 5 pages
Proc. SPIE 9818, 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage, 98180L (12 October 2016); doi: 10.1117/12.2245306
Show Author Affiliations
Xiaoyun Li, Shanghai Institute of Microsystem and Information Technology (China)
Houpeng Chen, Shanghai Institute of Microsystem and Information Technology (China)
Xi Li, Shanghai Institute of Microsystem and Information Technology (China)
Qian Wang, Shanghai Institute of Microsystem and Information Technology (China)
Xi Fan, Shanghai Institute of Microsystem and Information Technology (China)
Houpeng Chen, Shanghai Institute of Microsystem and Information Technology (China)
Xi Li, Shanghai Institute of Microsystem and Information Technology (China)
Qian Wang, Shanghai Institute of Microsystem and Information Technology (China)
Xi Fan, Shanghai Institute of Microsystem and Information Technology (China)
Jiajun Hu, Shanghai Institute of Microsystem and Information Technology (China)
Yu Lei, Shanghai Institute of Microsystem and Information Technology (China)
Qi Zhang, Shanghai Institute of Microsystem and Information Technology (China)
Zhen Tian, Shanghai Institute of Microsystem and Information Technology (China)
Zhitang Song, Shanghai Institute of Microsystem and Information Technology (China)
Yu Lei, Shanghai Institute of Microsystem and Information Technology (China)
Qi Zhang, Shanghai Institute of Microsystem and Information Technology (China)
Zhen Tian, Shanghai Institute of Microsystem and Information Technology (China)
Zhitang Song, Shanghai Institute of Microsystem and Information Technology (China)
Published in SPIE Proceedings Vol. 9818:
2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage
Fuxi Gan; Zhitang Song; Yang Wang, Editor(s)
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