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Proceedings Paper

Memory devices based on self-assembled materials and processes (Conference Presentation)
Author(s): Jang-Sik Lee

Paper Abstract

Device fabrication based on top-down approach will reach its limit due to difficulties in patterning and processes below 10 nm node. The bottom-up approach using self-assembled materials and processes can be a viable candidate for further device scaling, but the fabrication processes are mostly not compatible with current device fabrication. In this presentation, device fabrication strategy for next-generation data-storage devices will be discussed in detail based on self-assembled materials and processes. The emphasis is placed on compatibility with current device fabrication strategies. Ordered array of various materials and systems based on bottom-up nanotechnology can be utilized as the charge storage layer for memory devices and the templates for nanoscale device fabrication. Novel device applications, for example, printed/flexible/transparent electronic devices, will be explored based on the self-assembly processes.

Paper Details

Date Published: 7 November 2016
PDF: 1 pages
Proc. SPIE 9945, Printed Memory and Circuits II, 994505 (7 November 2016); doi: 10.1117/12.2238596
Show Author Affiliations
Jang-Sik Lee, Pohang Univ. of Science and Technology (Korea, Republic of)

Published in SPIE Proceedings Vol. 9945:
Printed Memory and Circuits II
Emil J. W. List-Kratochvil, Editor(s)

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