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Proceedings Paper

Three-dimensional functional integration in silicon using confined selective epitaxial growth
Author(s): Marian Bartek; Paul T. J. Gennissen; Reinoud F. Wolffenbuttel
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Paper Abstract

A Confined Selective Epitaxial Growth (CSEG) technique is optimized to produce 0.9 micrometers thick and up to 15 micrometers wide local SOI slabs, isolated from the (001) substrate by a low-stress silicon nitride. In the fabrication process, a cavity is formed above the silicon substrate with access to the monocrystalline silicon using surface micromachining techniques. Subsequently, during the selective epitaxial growth this cavity is filled with single crystal silicon. In previous works, oxide was used for the isolation layers, and amorphous silicon as the sacrificial material. Here, an improved method, where low-stress nitride layers are used as structural layers to confine the epitaxial growth and PSG is used as a sacrificial material, is presented. The lateral growth rates of up to 260 nm/min were used and a horizontal to vertical aspect ratio 16:1 achieved. In these local SOI silicon slabs, a standard BiFET process has been merged to investigate technical feasibility of the vertical on-ship integration of a silicon sensor and a microelectronic cavity. The emitter-base ideality factor of 1.03 and overall performance of the fabricated transistors are very promising and indicate excellent material quality of CSEG silicon, where the [100] seed window orientation is used.

Paper Details

Date Published: 26 September 1995
PDF: 10 pages
Proc. SPIE 2640, Microlithography and Metrology in Micromachining, (26 September 1995); doi: 10.1117/12.222648
Show Author Affiliations
Marian Bartek, Delft Univ. of Technology (Netherlands)
Paul T. J. Gennissen, Delft Univ. of Technology (Netherlands)
Reinoud F. Wolffenbuttel, Delft Univ. of Technology (Netherlands)

Published in SPIE Proceedings Vol. 2640:
Microlithography and Metrology in Micromachining
Michael T. Postek, Editor(s)

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