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Proceedings Paper • Open Access

Lithography alternatives meet design style reality: How do they "line" up?
Author(s): Michael C. Smayling

Paper Abstract

Optical lithography resolution scaling has stalled, giving innovative alternatives a window of opportunity. One important factor that impacts these lithographic approaches is the transition in design style from 2D to 1D for advanced CMOS logic. Just as the transition from 3D circuits to 2D fabrication 50 years ago created an opportunity for a new breed of electronics companies, the transition today presents exciting and challenging time for lithographers. Today, we are looking at a range of non-optical lithography processes. Those considered here can be broadly categorized: self-aligned lithography, self-assembled lithography, deposition lithography, nano-imprint lithography, pixelated e-beam lithography, shot-based e-beam lithography .Do any of these alternatives benefit from or take advantage of 1D layout? Yes, for example SAPD + CL (Self Aligned Pitch Division combined with Complementary Lithography). This is a widely adopted process for CMOS nodes at 22nm and below. Can there be additional design / process co-optimization? In spite of the simple-looking nature of 1D layout, the placement of “cut” in the lines and “holes” for interlayer connections can be tuned for a given process capability. Examples of such optimization have been presented at this conference, typically showing a reduction of at least one in the number of cut or hole patterns needed.[1,2] Can any of the alternatives complement each other or optical lithography? Yes.[3] For example, DSA (Directed Self Assembly) combines optical lithography with self-assembly. CEBL (Complementary e-Beam Lithography) combines optical lithography with SAPD for lines with shot-based e-beam lithography for cuts and holes. Does one (shrinking) size fit all? No, that’s why we have many alternatives. For example NIL (Nano-imprint Lithography) has been introduced for NAND Flash patterning where the (trending lower) defectivity is acceptable for the product. Deposition lithography has been introduced in 3D NAND Flash to set the channel length of select and memory transistors.

Paper Details

Date Published: 22 March 2016
PDF: 6 pages
Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 977702 (22 March 2016); doi: 10.1117/12.2224685
Show Author Affiliations
Michael C. Smayling, Tela Innovations, Inc. (United States)

Published in SPIE Proceedings Vol. 9777:
Alternative Lithographic Technologies VIII
Christopher Bencher, Editor(s)

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