Standard cell pin access has become one of the most challenging issues for the back-end physical design in sub-14nm technology nodes due to increased pin density, limited number of routing tracks, and complex DFM rules/constraints from multiple patterning lithography. The standard cell I/O pin access problem is very difficult also because the access points of each pin are limited and they interfere with each other. There have been several studies across various standard cell and physical design stages, including standard cell pin access optimization, placement mitigation and routing planning, to achieve overall pin access optimization. In this paper, we will introduce a holistic approach across different design stages to deal with the pin access issue while accommodating the complex DFM constraints in advanced lithography.

Date Published: 15 March 2016
PDF: 13 pages
Proc. SPIE 9780, Optical Microlithography XXIX, 97800P (15 March 2016); doi: 10.1117/12.2222289

Published in SPIE Proceedings Vol. 9780:
Optical Microlithography XXIX
Andreas Erdmann; Jongwook Kye, Editor(s)