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Proceedings Paper

Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing
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Paper Abstract

At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.

Paper Details

Date Published: 16 March 2016
PDF: 12 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978109 (16 March 2016); doi: 10.1117/12.2220145
Show Author Affiliations
Piyush Pathak, GLOBALFOUNDRIES Inc. (United States)
Karthik Krishnamoorthy, GLOBALFOUNDRIES Inc. (United States)
Wei-Long Wang, GLOBALFOUNDRIES Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Frank E. Gennari, Cadence Design Systems, Inc. (United States)
Shikha Somani, GLOBALFOUNDRIES Inc. (United States)
Bob Pack, GLOBALFOUNDRIES Inc (United States)
Uwe Paul Schroeder, GLOBALFOUNDRIES Inc. (United States)
Fadi Batarseh, GLOBALFOUNDRIES Inc. (United States)
Jaime Bravo, GLOBALFOUNDRIES Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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